Method and apparatus for generating a wafer map

ABSTRACT

A system is provided to aid in laying out circuits on a semiconductor wafer, in which a wafer map is automatically generated when entering chip sizes, arrangements and other enterable factors, with a goal to maximize yield probability. The subject system accommodates different chip types and arrangements within a wafer map and addresses edge exclusion, utilization of chiplets and accommodation of different centering techniques, including a variety of ways of measuring offsets, while outputting a display of replicated circuits on the wafer as well as chip count and density, utilizing a portable, tailorable, extendable PC-based program featuring an easy-to-use graphical interface. The software application provides a user with different graphical views customized for different process areas, such as lithography and dicing, with the application being useful for any semiconductor manufacturing facility, foundry or similar industry that needs to generate wafer maps automatically to maximize yield probability.

FIELD OF THE INVENTION

This invention relates to wafer design and fabrication and moreparticularly to an automatic design system for replicating circuitsacross a wafer.

BACKGROUND OF THE INVENTION

The capability of pattern 20 to 40 levels on wafers has resulted in theability to fabricate large numbers of integrated circuits on a singlewafer and to dice the wafer so as to provide individual integratedcircuits or combinations of circuits.

Typically in wafer fabrication, a stepper is utilized whichphotographically replicates or reproduces a particular pattern of alayer for an integrated circuit across the wafer in a stepped fashion sothat identical circuits can be fabricated across a given wafer.

For instance, taking a first metalization layer, one must first take apicture of the layer for the first chip to be replicated. One must thenstep to the next place where one wants to place a copy of themetalization layer, open the shutter and take the picture and then stepto the next place in a step-and-repeat process performed by a so-calledstepper. A photomask for microlithography is typically a quartz tile aquarter-inch thick and is covered with chrome. The chrome is thencovered with photo-resist and, for a given level, a pattern is writtenonto the photo-resist and then the chrome is etched. When this tile isflipped upside down, it becomes a chrome-on-glass master mask for thatparticular level. One might have 20 to 40 of these master masks perdevice, depending on the number of levels required. With the masks, onegoes layer by layer to build up the chip.

However, every time, one has to manually come back to photo and lay outthe chips on the wafer in a desired pattern. It is noted that oftentimes one puts down product chips at certain locations and then testchips or other product chips on the same wafer.

In terms of the design of a chip pattern on a wafer, the photo toolingthat is capable of adequate resolution and overlay does not have thefield size to be able to print the entire wafer at once.

To simplify, the mask contains a pattern for the circuitry for just onechip or if small enough for several chips or “chiplets”. Sometimes thecomplete integrated circuit is small enough to fit more than one chipimage on a mask and subsequent exposure field. These are then referredto as “chiplets” for the purposes of wafer layout. With a wafer having asix-inch diameter, the wafer can accommodate 20 or more of theseexposure fields. One first designs the chip, then fractures the data,then has a mask manufacturer write the data to a series of masks, withthe artwork being replicated, for instance, 40 times for the 40 chipsthat are to be placed on the wafer.

Just designing a single chip and providing the photolithography andmanufacturing step for the chip, while indeed complicated, is furthercomplicated when one wants to replicate the process across a wafer andmake efficient use of wafer real estate to be able to place the maximumnumber of chips on a given-size wafer. The chip designers then defer tothe photo layout engineers, who manually create a pattern of the tile isflipped upside down, it becomes a chrome-on-glass master mask for thatparticular level. One might have 20 to 40 of these master masks perdevice, depending on the number of levels required. With the masks, onegoes layer by layer to build up the chip.

However, every time, one has to manually come back to photo and lay outthe chips on the wafer in a desired pattern. It is noted that oftentimes one puts down product chips at certain locations and then testchips or other product chips on the same wafer.

In terms of the design of a chip pattern on a wafer, the photo toolingthat is capable of adequate resolution and overlay does not have thefield size to be able to print the entire wafer at once.

To simplify, the mask contains a pattern for the circuitry for just onechip or if small enough for several chips or “chiplets”. Sometimes thecomplete integrated circuit is small enough to fit more than one chipimage on a mask and subsequent exposure field. These are then referredto as “chiplets” for the purposes of wafer layout. With a wafer having asix-inch diameter, the wafer can accommodate 20 or more of theseexposure fields. One first designs the chip, then fractures the data,then has a mask manufacturer write the data to a series of masks, withthe artwork being replicated, for instance, 40 times for the 40 chipsthat are to be placed on the wafer.

Just designing a single chip and providing the photolithography andmanufacturing step for the chip, while indeed complicated, is furthercomplicated when one wants to replicate the process across a wafer andmake efficient use of wafer real estate to be able to place the maximumnumber of chips on a given-size wafer. The chip designers then defer tothe photo layout engineers, who manually create a pattern of the desiredchips across the wafer, which involves the pattern of the chip placementon the actual wafer.

While there exist steppers, such as provided by ASML of the Netherlands,what these steppers do are to step out pictures across the surface ofthe wafer in a pattern manually determined by the layout engineer.

However, the software for the steppers is relatively simplified anddoesn't take into account the fact that one may wish to replicatedifferent chips across the wafer and does not, for instance, take intoaccount how to maximize the density of the chips, given the type ofchips and placement one wishes. The stepper does not provide for agraphical interface which, aside from laying out the individual chips,accommodates such things as edge exclusion zones or edge areas that,while not being able to accommodate a full-sized chip, may nonethelessbe utilized to fabricate so-called chiplets. Thus, with the stepper typeof systems, there is no way to maximize the yield by being able torecognize that chiplets are possible, with the chiplets beingmanufacturable at the same time as the chips or full exposure field.

There is therefore a need for a system which allows the designer toenter in various parameters, such as wafer size, edge exclusion,flat-edge exclusion, periodicity in X and Y directions, and offsets in Xand Y directions.

Also, when the integrated circuit chip is composed of a number ofintegrated circuits, oftentimes each of this number of integratedcircuits can be characterized as a chiplet. Thus, when there is notenough room on a wafer for a complete chip, chiplets can be positionedon the wafer so they can be manufactured at the same time that the chipsare manufactured. There is therefore a need for the layout engineer tobe able to specify the location of these chiplets on the wafer, whichinvolves specifying the number of chiplet rows and the number of chipletcolumns. Moreover, it is important for the layout engineer to be able tospecify the wafer type, meaning whether or not the wafer is notched orflat.

As will also be appreciated, there needs to be a way for the maskengineer to be provided with a wafer map or visual representation ofwhere the chips and chiplets are on a wafer. Also there is a requirementto permit the designer to enter in field parameters, such as UsableField attributes, Edge Field attributes and chiplet attributes.

Most importantly, there needs to be a graphical interface to be able tovisually present to the wafer designer the placement of the variouschips and chiplets, the areas which have the Usable Fields withcircuits, or Edge Fields, which may or may not have circuits on them, aswell as to indicate the number of chips and chiplets that are achievablewith a given pattern. Note that a useable field is a field in which theoutline of the chip does not touch the edge exclusion ring for thewafer, whereas an Edge Field is one in which at least a portion of thechip is in the exclusion region.

With such a handy tool in place, the wafer designer may lay out wafersnot only by simply brute force replicating chips across a wafer, butrather placing them, organizing them in terms of the offset and othercharacteristics of the chips themselves, by defining chiplets andplacing them at points where an edge exclusion does not affect theformation of the chiplet, and then by presenting the wafer designer witha chip count for his or her design.

SUMMARY OF INVENTION

Rather than manually laying out a pattern of chips on a wafer, in thesubject system the pattern is automatically generated by filling out anumber of fields on a web page, in one embodiment, and having the systemcalculate the arrangement of the chips and chiplets and present to thedesigner the results of the arrangement in terms of a wafer map, alongwith the chip count achieved by the particular pattern.

In one embodiment, the designer is presented with a normal view of thelayout of the chips as automatically performed; a stepper view, meaninghow the layout is viewed by the stepper in terms of providing forreplicated photographs of the various layers across the chip; and also adicing view in which the designer can see how the wafer can be diced upto provide for the individual fabricated chips or chiplets.

Aside from predetermining the size of the chip or chiplets, one canreview the results of an automatic operation when a chip is centered,when a chip corner is centered, when a chip side is centered, when thecenter of a chip is offset, and when a corner of a chip is offset. Onecan also specify the offsets in each of these cases and be presentedwith a result that visually indicates the automatically generated layoutof the chips on the wafer.

The functionality of the subject system and its software to maximallylay out chips or chiplets on a wafer in a way that allows the designerto change various parameters such as edge exclusion, chip size,periodicity, grid offset, chiplet size, and wafer size. The systemallows the designer to input chiplet dimensions in rows and columnswithin an exposure field. It also gives the designer graphical viewscustomized for the different process areas such as lithography anddicing.

The result is a software application that generates a wafer layout mapby inputting differing chip sizes, periodicities, arrangements, wafersizes, edge exclusions, views, chip sites, chip types, and chipletsizes. The application also calculates the number of chips and chipletsof each type that are laid out on a given wafer. The applicationgraphically displays the wafer maps and allows designers tointeractively change the parameters to suit their process needs.

Note that once the wafer has been laid out, the wafer design may bepassed as a data set to a commercial stepper such as the ASML stepper.

In one embodiment, the wafer designer first provides input parametersenterable at the designer's screen or from a database. The applicationthen determines Usable Fields, determines Edge Fields, and determineschiplets within Edge Fields. Thereafter, the application initializes thestate of usable and Edge Fields, initializes the state of chipletswithin the Edge Fields and initializes the edge exposure region. Thesystem then computes the chip counts and draws a pattern of UsableFields, Edge Fields, chiplets and the edge exclusion region.

Once being provided with a normal view, the wafer designer can updatethe pattern by placing a cursor on an x-y position. The application thensearches for a Usable Field that bounds the cursor x-y position. If aUsable Field is found, then the application updates the state of UsableFields and updates the chip counts. If no Usable Field is found, meaningthat a field touches the edge exclusion region, then the applicationsearches for Edge Fields that bound the cursor x-y position. An EdgeField is one in which there is some room to put down a chiplet withoutviolating the edge exclusion region, but not enough room for a completechip. If no Edge Field is found, the process ends. If an Edge Field isfound, then the application decides whether or not there are chipletscontained in the Edge Field. If there are chiplets contained, then theapplication updates the state of the chiplets and updates the chipcount. If there are no chiplets, again, the state of the Edge Field isupdated and there is an update in chip counts.

A user can thus enter and thereby generate wafer layout mapsautomatically by entering the desired parameters in a web-based orstandalone program. The user can also designate chiplet offsets or varythe orientations of the chips or chiplets. The user obtains the wafermap that automatically maximizes yield probability, distinguishesbetween chip types and can view maps in different modes.

The subject system thus solves the problem where no commercial softwareis available to create wafer maps showing chip sizes, arrangements andmaximizing yield probability. While in the past wafer maps had to becreated manually based on engineering judgment for maximum yieldprobability, the subject system now does so automatically. While in thepast it was not possible to address different chip types or arrangementswithin a wafer map, one can now do so while at the same time addressingedge exclusion properties, chiplets, offsets, and to present the datawith different map viewing capabilities.

The result is a portable, tailorable, extendable system that can be runon a desktop PC or as a web-based program featuring an easy-to-usegraphical interface. The subject system provides exceptionalfunctionality, allowing designers to change various parameters and evenallows the designer to input chiplet dimensions in rows and columnswithin an exposure field. The subject system also provides the designerwith different graphical views customized for different process areasand is very useful for any semiconductor manufacturing facility,foundry, or similar industry that needs to generate wafer mapsautomatically to maximize yield probability.

In summary, a system is provided to aid in the laying out of circuits ona semiconductor wafer, in which a wafer map is automatically generatedwhen entering chip sizes, arrangements and other enterable factors, withthe goal to maximize yield probability. The subject system accommodatesdifferent chip types and arrangements within a wafer map and addressesedge exclusion, the utilization of chiplets and the accommodation ofdifferent centering techniques, including a variety of ways of measuringoffsets, while outputting a display of the replicated circuits on thewafer as well as chip count and density, utilizing a portable,tailorable, extendable PC-based program featuring an easy-to-usegraphical interface. The software application provides the user withdifferent graphical views customized for the different process areas,such as lithography and dicing, with the application being useful forany semiconductor manufacturing facility, foundry or similar industrythat needs to generate wafer maps automatically to maximize yieldprobability.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of the subject invention will be betterunderstood in connection with a Detailed Description, in conjunctionwith the Drawings, of which:

FIG. 1 is a diagrammatic illustration of an individual utilizing thesubject system to generate a wafer map, the output of which, in turn,could be coupled to a stepper;

FIG. 2 is a diagrammatic illustration of the wafer map generated in FIG.1, including the layout of the individual chips and chiplets as well asthe display of a chip count to indicate yield;

FIG. 3 is a screen shot of the computer of FIG. 1, illustrating fieldsin which data relating to wafer size, periodicity, chiplet rows, chipletsize and offsets in orthogonal directions may be entered;

FIG. 4 is a screen shot of the computer of FIG. 1, illustrating chiplayouts used in determining centering, providing selectability for chipcenter centering, chip corner centering, chip side centering in eitherthe x or y direction, chip center offsetting or chip corner offsetting,also indicating that with a change in centering, a different number ofchips can be laid out on a wafer;

FIG. 5 is a screen shot of a normal view of the chip layout, indicatinga number of chips that exist in Usable Fields, a number of chips which,through the utilization of chiplets, exist in an Edge Field for which atleast some region is free of edge exclusion constraints and in which anedge exclusion region for the wafer is shown;

FIG. 6 is a screen shot of the stepper view for the wafer layout;

FIG. 7 is a screen shot of the computer of FIG. 1, illustrating that fora given wafer map, dicing lines are shown indicating where the wafer maybe scribed so that individual chips or chiplets may be broken off;

FIG. 8 is a flow chart showing how input parameters are treated in termsof determining Usable Fields, usable Edge Fields, chiplets within EdgeFields, initialization states and the initialization of edge exposureregions, followed by the computation of chip counts and the drawing ofUsable Fields, Edge Fields, chiplets and edge exposure regions, givenselected parameters; and,

FIG. 9 is a flow chart illustrating how to update the normal view of thewafer map so as to be able to include more chips or chiplets, thus to beable to update the wafer map and the parameters, and to calculate chipcounts associated therewith.

DETAILED DESCRIPTION

Referring now to FIG. 1, rather than manually laying out a wafer map andrather than utilizing the normal stepper software to provide a waferlayout, in the subject invention, an individual 10 at a keyboard 12 forcomputer 14 views a display screen 16 and enters in various parametersrelating to the wafer map the individual seeks to generate. The wafermap, which is the layout of the chips or chiplets on a wafer, specifiesthe number of chips that can be successfully laid out, given the areaand the size of the chips or chiplets that are to be fabricated onto thespecified wafer.

In the past it was assumed that all the chips were to be of the samesize and of the same functionality, such that they were simply laid outin a standard format. However, it is possible to increase the density ona given wafer for the integrated circuits utilized by understanding thatsome of the integrated circuits are made up of different subcomponentsor circuits, herein referred to as chiplets, and by changing otherparameters such as centering. By arranging the wafer map, taking into anaccount an exclusion zone or region around the periphery of the waferand being able to visually ascertain where a particular layout touchesor infringes upon the exclusion region, one can optimally andautomatically lay out a wafer by placing of the chips and the chipletsfor maximum benefit.

After the computer has performed the appropriate calculations, CPU 14generates a wafer map 18, the data from which is coupled to stepper 20,which then provides the stepped photography to be able to generate masks22.

Referring to FIG. 2, wafer map 18 generated by CPU 14 is displayed interms of a wafer 24 having chips or chiplets 26 arrayed across the faceof the wafer in accordance with calculations automatically done by CPU14. The layout of the chips and chiplets is referred to as the wafermap. The display at least in one instance provides a chip count so thatindividual 10 can ascertain at a glance whether or not the parametersthat he has inputted by means of keyboard 12 into fields presented tohim on display 16, have in fact increased or decreased the chip count.If the chip count has not been increased to the individual'ssatisfaction or has in fact decreased, the individual can again re-enteror change the parameters inputted to CPU 14 so that the individual canmanipulate the parameters to achieve a desired density or layout of thechips or chiplets on the wafer.

Table I is a listing of product parameters and field parameters that areinputtable by individual 10 to generate the automatic chip or chipletlayout. The product parameters are specified by the user for new wafermaps or are retrieved from a database for existing wafer maps. The fieldparameters are retrieved from the database for existing wafer maps only.

TABLE I APPLICATION INPUT PARAMETERS Product Parameters specified byuser (new wafer maps) or retrieved from database (existing wafer maps):Product Name Product name associated with the wafer map. Wafer SizeWafer map diameter (in mm). Edge Exclusion Size of wafer map edgeexclusion region (in mm). Flat Edge Exclusion Wafer map flat edgeexclusion. Periodicity X Periodicity X value (in mm). Periodicity YPeriodicity Y value (in mm). Offset X Wafer map x-offset from centervalue (in mm). Offset Y Wafer map y-offset from center value (in mm).Number of Chiplet Rows Maximum number of chiplet rows per Edge Field.Number of Chiplet Cols Maximum number of chiplet columns per Edge Field.Scale Factor Factor used in scaling the wafer map. Wafer Type Type ofwafer map (notched or flat). Field Parameters Retrieved from Database(existing wafer maps only): Usable Field Attributes Upper left and lowerright (x, y) positions, state, and quadrant. Edge Field AttributesMaximum upper and lower (x, y) positions, state, and quadrant ChipletAttributes Upper left and lower right (x, y) positions, state, andquadrant.

What will be seen is that at the user's discretion he can specify thewafer size, the edge exclusion region or zone, the flat edge exclusionregion, periodicity in the x and y directions as well as offsets in thex and y directions, together with the number of chiplet rows and columnswhich refers to the maximum number of chiplet rows and columns per EdgeField. The individual can also enter into the system a scale factor usedin scaling the wafer map and the wafer type, meaning whether it isnotched or flat.

It will be appreciated that by being able to enter various parametersinto the system before the automatic layout of the chips and chiplets toprovide the wafer map, one can fine-tune or increase productivity bybeing able to see at a moment's glance the effect of the changes of theparameters and the resulting chip count so as to be able to know theeffect of a given change in the parameters.

It is also possible to identify both chips and chiplet types so that onecan specify what constitutes a chiplet and be able to place it at anappropriate position in the wafer map so as to maximize not only thenumber of chips that can be accommodated by the wafer but also thenumber of chiplets.

Referring now to FIG. 3, the screen shot indicates a product name may beassigned in field 30, a stepper name in field 32 and as to the wafer mapdata, the wafer size as illustrated in field 34. The user can specifythe edge exclusion zone or region in field 36 and the x periodicity infield 38 as well as the y periodicity in field 40.

One can also set the maximum number of chiplet rows as illustrated infield 42 and the maximum number of chiplet columns as illustrated in 44,whereas in field 46 one can set the chiplet size in the x direction andin field 48 the chiplet size in the y direction. One can also specify infield 50 the x offset and in field 52 the y offset. Clickable regions 54for submit, 56 for calculate, 58 for reset and 60 for going back makethe subject system user friendly.

Referring now to FIG. 4, what is presented to the user on display 16 isthe effect of particular centering procedures and offset procedures. Asillustrated at 62, a series of chips 64 are shown arranged such that thecenter of chip 64′ is centered in the crosshairs 65 of the system. Itwill be noted that the system calculates the number of chips arrangeablewithin a given wafer and displays it in field 66 with the click of apreview button 63.

Should, for instance, a chip corner be desired to be centered, then asillustrated at 70, the corner of chip 72 is centered in crosshairs 65 asillustrated, and the resulting number of chips with this type ofarrangement is displayed at field 74. Again, the view is presented bythe clicking on the preview button 63.

If one chooses to center the chip on a horizontal side or edge, then asillustrated at 80, chips 82 are indicated as having their horizontaledge centered along the horizontal crosshair, with the number of chipsassociated with such a centering arrangement illustrated in field 84,again through clicking on the preview button 63.

On the other hand, if it is desired to center the chips on a verticaledge as illustrated at 90, then chips 92 are shown centered along thevertical crosshair, with the corresponding number of chips to beproduced by such a centering illustrated in field 94, again throughclicking the preview button 63.

Another way of potentially increasing the yield for the wafer is tooff-center the entire chip map by off-centering or offsetting the centerof a chip as illustrated at 100, with chip 102 being off-centered incrosshairs 65, with the number of chips for this arrangement being shownin field 104, again with a clicking of preview button 63.

If on the other hand it is desired to offset a corner of chips asillustrated at 110, then chips 112 will have their corners offset withrespect to crosshairs 65 and, as illustrated in field 114, the number ofchips will be calculated upon clicking preview button 63.

Referring now to FIG. 5, display 16 of FIG. 1 shows a rendering of thewafer map in which in the normal view, the periphery of the wafer 120 isshown with an edge exclusion region 122. This region refers to the factthat no chips or chiplets can be successfully laid out in this area,since the area is so close to the periphery of the wafer. Laid outwithin the exclusion zone or region are a number of Usable Fields 124,which are designated with letters A, C, D and TS. Shown on the screen atthe upper portion are the parameters entered.

Here, A refers to a chip that may include a number of individualintegrated circuits, as do chips C and D. These chips are arrayed in across-like fashion so that, at least as far as the Usable Fields areconcerned, they all fit and do not touch the edge exclusion region.Thus, the term Usable Field means that, for a chip of a given size, itcan be located in a Usable Field without fear of intruding upon the edgeexclusion region.

Also indicated in this figure are Edge Fields 126, which refers to areasor fields, some of which touches the exclusion region.

There are some Edge Fields, such as indicated at 128, for which nosubdivided chips or chiplets can be manufactured. This is simply becausethere is not enough space to provide for a subdivided circuit orchiplet. However, as can be seen at 130, a chiplet, which is asubdivided portion of a chip, can successfully be located on the waferwithout touching the edge exclusion region. For this reason, it ispossible to lay out a wafer so as to provide usable space for chipletsas opposed to the chips themselves, which are larger.

For instance, if a chip is a field-programmable gate array (FPGA) thatincludes a number of separate circuits, to increase yield one may wishto fabricate several of the separate circuits on the same wafer as thetotal FPGA chips, thus to make use of the available space. One thereforedesignates the so-called chiplets, which are smaller in size than theFPGA chips themselves.

The result of the subject system is that on can visually represent thewafer layout or design with a program that will locate not only chips ofa given size but also chiplets of a given size so that they can besuccessfully patterned onto the wafer without violating the edgeexclusion region or zone.

Referring to FIG. 6, display 16 can be made to display the stepper viewof the data outputted from the wafer-mapping application. Here it can beseen that from the stepper point of view, the stepper recognizes chipsin Usable Fields such as chips 140, which are designated by capitalletters. The designation E refers to areas in which chiplets do notexist in an Edge Field.

Referring to FIG. 7, as illustrated at 150, a dicing view of the wafermap of FIG. 5 is shown in which it can be readily seen that a chip iseither in a Usable Field or an Edge Field. Here chip 152 labeled A₀ isin a Usable Field. However, chiplets 154, also labeled A₀, exist in anEdge Field. It is also noted that, since one can subdivide chip A intosubcomponents or chiplets A₀, these chiplets will be manufactured wherepossible within an edge exclusion zone or region such that chiplets 154can be produced at the same time their corresponding chips 152 areproduced.

In this figure, the scribe lines for dicing, here shown at 160, areshown so as to give the individual 10 of FIG. 1 an idea of how the waferthat he has designed can be diced into individual product. Also, shownin the dicing view of FIG. 7 is that there are invalid zones 166 forwhich no chips or chiplets will be available.

Here it takes some designer skill to be able to look at a chip and seewhat useful subcircuits can be manufactured at the same time as thecorresponding chip.

Referring now to FIG. 8, in terms of the application flow at startup,individual 10 gets input parameters from the user screen or database asillustrated at 170. The system then determines Usable Fields asillustrated at 172 and Edge Fields, as illustrated at 174. The UsableFields are calculated from the size of the chips, whereas the EdgeFields are calculated as being those fields that contain chips but thattouch the edge exclusion region.

The system then determines if it is possible to have chiplets within theEdge Fields of 174 as illustrated at 176 and, as illustrated at 178,provides an initialized state of usable and Edge Fields and aninitialized state of chiplets within those fields. The state of a fieldrefers whether or not it is to be exposed and, if exposed, the type ofchips contained in the region. The states of the Usable Fields withinthe wafer map are initialized to indicate exposed regions of productchips on the wafer map. The initial states of Edge Fields for the wafermap depends on whether chiplets are contained within its boundary. ForEdge Fields that have chiplets, the initial states are set to displayexposed regions of product chiplets on the wafer map. For Edge Fieldsthat do not contain chiplets, the initial states are set to showunexposed regions on the wafer map.

As illustrated at 180, the system initializes the edge exposure regionbased on the a priori knowledge of the wafer. In this contextinitializing an edge exclusion region means setting the initial state ofEdge Fields that do not contain chiplets.

After the application arranges all of the chips and chiplets, theapplication computes chip counts as illustrated at 182.

After the system lays out the chips and chiplets, given the parametersentered, the system draws a pattern of Usable Fields, Edge Fields,chiplets and the Edge Exclusion Region as illustrated at 184.

Referring to FIG. 9, if individual 10 of FIG. 1 seeks to update orchange the normal view he is presented with, then with a mouse, theindividual sets a cursor on an x and y position as illustrated at 186,at which point a search at 188 is performed for a Usable Field thatbounds the cursor x-y position. As illustrated at 190, if there is aUsable Field found, then as illustrated at 192 the system updates thestate of the Usable Fields and updates the chip counts, at which pointthe system stops as illustrated at 194. If no Usable Field is found at190 for a particular x-y position of a chip, then a search is performedat 196 for an Edge Field that bounds the cursor x-y position. If an EdgeField is found as illustrated at 198, then a determination at 200 ismade as to whether or not the Edge Field contains chiplets. If so, asillustrated at 202, there is an update of the state of the chiplets andan updated chip count, at which point the process stops as illustratedat 204.

If there are no chiplets in the particular Edge Field found, then thesystem updates the state of the Edge Field, as illustrated at 206 andupdates the chip counts, at which point the process ends as illustratedat 204.

What is now presented is a program listing in Java that describes thegeneration of the wafer map in all of its forms, given the variousinputs described above.

While the present invention has been described in connection with thepreferred embodiments of the various figures, it is to be understoodthat other similar embodiments may be used or modifications or additionsmay be made to the described embodiment for performing the same functionof the present invention without deviating therefrom. Therefore, thepresent invention should not be limited to any single embodiment, butrather construed in breadth and scope in accordance with the recitationof the appended claims.

1. A method for aiding in laying out a number of integrated circuitchips on a semiconductor wafer, comprising steps of: automaticallygenerating a wafer map taking into account predetermined parameters, thewafer map automatically maximizing the number of integrated circuitchips to be laid out on a predetermined size wafer; displaying theautomatically generated wafer map including displaying type of chip withthe chip being divided into chiplets; and, displaying indiciarepresenting chiplets.
 2. The method of claim 1 further including a stepof using the automatically generated wafer map to control a stepper. 3.The method of claim 2, wherein the stepper photographically replicatespatterning of images of an integrated circuit for a number of chips ontophotoresist carried by the semiconductor wafer so as to replicate thepattern for a layer of the integrated circuit such that the pattern isreproduced across the semiconductor wafer in accordance with the wafermap.
 4. The method of claim 1, wherein the predetermined parametersinclude wafer size.
 5. The method of claim 1, wherein the predeterminedparameters include chip size.
 6. The method of claim 1, wherein thepredetermined parameters include an exclusion zone for the semiconductorwafer.
 7. The method of claim 1, wherein the predetermined parametersinclude centering type.
 8. The method of claim 7, wherein the centeringtype parameter includes offset.
 9. The method of claim 8, wherein thecentering type is selected from a group consisting of chip centercentered, chip corner centered, chip side centered, chip offset centeredand chip offset corner centered centering types.
 10. The method of claim1 further including a step of displaying the automatically generatedwafer map.
 11. The method of claim 10, wherein the displaying stepincludes displaying a stepper view.
 12. The method of claim 10, whereinthe displaying step includes displaying a dicing view.
 13. The method ofclaim 10, wherein the displaying step includes displaying a view of thesemiconductor wafer map on the wafer as the chips represented by thesemiconductor wafer map would appear on the semiconductor wafer.
 14. Themethod of claim 10 further including a step of displaying usable fields.15. The method of claim 10 further including a step of displaying edgefields.
 16. The method of claim 10 further including a step ofindicating invalid layout regions for chips.
 17. The method of claim 16further including a step of displaying an edge exclusion region, andwherein an invalid layout region is one in which a portion of a chiplies in the edge exclusion region.
 18. The method of claim 10 furtherincluding a step of displaying type of chip.
 19. The method of claim 1further including a step of displaying indicia indicating invalidchiplets.
 20. The method of claim 1 further including a step ofdisplaying a chip count for the automatically generated wafer map, thusto display result of the automatically generated wafer map.
 21. Themethod of claim 20 further including steps of: altering thepredetermined parameters to obtain modified parameters; and displayingchip count result for the modified parameters, thus to permit maximizingutilization of wafer real estate by selection of parameters forautomatic wafer mapping.